Course Content
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1 – Introduction
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1 – Introduction
00:35
2 – Course coverage
05:53
4 – Quick CMOS basics added as per request_part1
19:52
4 – Quick CMOS basics added as per request_part2
19:52
5 – What is VLSI
01:55
6 – Review of terms
02:36
7 – Minimum feature size
00:48
8 – Why Integration
03:55
9 – Broad areas in VLSI
11:19
10 – VLSI Design Styles Full Custom
07:37
11 – VLSI Design Styles Semi Custom
03:17
12 – VLSI Design Styles FPGA
04:54
13 – VLSI Design Styles Gate Array
02:08
14 – VLSI Design Styles Comparison
04:22
15 – Full custom vs Semi custom
03:11
16 – ASIC vs FPGA
04:05
17 – ASIC Design Flow Part 1
13:29
18 – ASIC Design Flow Part 2
05:39
19 – ASIC Design Flow Design Specs
02:44
20 – ASIC Design Flow Architecturing
03:27
21 – ASIC Design Flow RTL coding
01:23
22 – ASIC Design Flow Verification
03:48
23 – ASIC Design Flow Synthesis
04:42
24 – ASIC Design Flow Design for Testability
08:03
25 – ASIC Design Flow Timing Analysis
02:26
26 – ASIC Design Flow Floorplanning Placement & Routing
03:44
27 – ASIC Design Flow Formal Verification
01:14
28 – ASIC Design Flow Power Estimation
01:22
29 – ASIC Design Flow Fabrication
00:22
30 – ASIC Design Flow Packaging
01:16
2 – Verilog Basics
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31 – Verilog Design Styles
02:52
32 – My First Dataflow Style Design
07:47
33 – My First Behavioral Style Design
06:55
34 – My First Structural Style Design
06:05
35 – 1bit Full Adder Sturctural1
08:08
36 – 1bit Full Adder Sturctural2
05:53
37 – 1bit Full Adder Sturctural3
05:56
38 – 1bit Full Adder Dataflow
02:33
39 – 1bit Full Adder Behavioral
02:39
40 – My first Test Bench
14:15
3 – Designing Combinational Logic
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41 – 4 Valued Logic
16:42
42 – Data Types
04:33
43 – Number Representation
13:22
44 – Bit and Bus
04:42
45 – Naming Conventions
03:42
46 – Operators Bitwise
17:19
47 – Operators Arithmetic
16:01
48 – Operators Logical
16:51
49 – Operators Relational
07:24
50 – Operators Reduction
10:56
51 – Operators Shift
08:37
52 – Operators Concatenation
04:15
53 – Operators Repetition
02:08
54 – Operators Conditional
04:03
55 – Output Resolution Table
10:40
56 – 4bit Full Adder Structural
06:13
57 – 4bit Full Adder Dataflow
01:56
58 – 4bit Full Adder Behavioral
01:26
59 – 4bit Full Adder Test Bench
08:37
60 – 21 Multiplexer Dataflow
02:23
61 – 21 Multiplexer Behavioral
04:07
62 – 41 Multiplexer Dataflow1
02:22
63 – 41 Multiplexer Dataflow2
06:47
64 – 41 Multiplexer Dataflow3
03:15
65 – 41 Multiplexer Behavioral
03:44
66 – 2 X 4 Decoder Dataflow
05:31
67 – 2 X 4 Decoder Behavioral
05:22
68 – 3 X 8 Decoder Dataflow
01:22
69 – 4 X 2 Encoder Dataflow
06:50
70 – 4 X 2 Encoder Behavioral
08:33
71 – 4 X 2 Priority Encoder Behavioral
05:45
72 – 4 X 2 Priority Encoder Dataflow
04:22
73 – 4bit Comparator Dataflow 1
06:44
74 – 4bit Comparator Dataflow 2
03:41
75 – 4bit Comparator Behavioral
00:58
76 – 8bit Barrel Shifter Combinational Left & Right
20:22
77 – Designing Arithmetic & Logic Unit ALU
08:02
4 – Designing Sequential Logic
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78 – Clock DLatch and a DFlip Flop
09:07
79 – DFlip Flop vs DLatch
07:48
80 – DLatch Dataflow
02:11
81 – DLatch Behavioral
01:49
82 – DLatch with Asynchronous Reset Behavioral
01:31
83 – DFlip Flop Basic
05:31
84 – Postitive Edge Triggered DFlip Flop with Asynchronous Active High Reset
05:10
85 – Negative Edge Triggered DFlip Flop with Asynchronous Active High Reset
03:21
86 – Postitive Edge Triggered DFlip Flop with Asynchronous Active Low Reset
01:33
87 – Postitive Edge Triggered DFlip Flop with Asynchronous Active High Set
02:55
88 – Synchronous DFlip Flop with Active High Reset
02:54
89 – Synchronous DFlip Flop with Active Low Reset
00:48
90 – Synchronous DFlip Flop with Reset and Set
01:37
91 – Synchronous and Asynchronous Reset Design
10:48
92 – 8bit Twin Register Set
03:28
93 – Designing a 5bit Left to Right Shift Register
11:07
94 – Designing a 5bit Universal Shift Register
06:01
95 – Designing a basic counter
03:58
96 – Writing a Test Bench for a Counter
02:55
97 – Designing an Up Counter with Load Option
02:53
98 – Designing an Up or Down Counter
02:35
99 – Designing a Modulus Counter
03:56
100 – Designing a Range Up Counter
03:57
101 – Designing a Range Up or Down Counter with Load Option
08:49
102 – Designing a Clock Frequency Divider Divide by 2
04:09
103 – Designing a Clock Frequency Divider Divide by 4
03:54
104 – Designing a Clock Frequency Divider Divide by 3
08:41
105 – Designing a Single Clock First In First Out FIFO
24:40
106 – Designing a Dual Clock First In First Out FIFO
07:07
5 – Designing Memories
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107 – Memory Array Options and Definitions
13:10
108 – Single Port Ram v1
07:50
109 – Single Port Ram v2
02:28
110 – Single Port Ram v3
02:56
111 – Single Port Ram v4
01:29
112 – Dual Port Ram v1
03:36
113 – Dual Port Ram v2
01:36
114 – True Dual Port Ram v1
06:05
115 – True Dual Port Ram v2
03:33
6 – Designing Finite State Machines
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116 – Mealy vs Moore Machine
06:20
117 – Mealy 101 NonOverlapping Sequence Detector
04:14
118 – Mealy 011 NonOverlapping Sequence Detector
01:59
119 – Mealy 000 NonOverlapping Sequence Detector
01:54
120 – Mealy 0101 NonOverlapping Sequence Detector
02:26
121 – Mealy 11011 NonOverlapping Sequence Detector
02:37
122 – Mealy 101 Overlapping Sequence Detector
02:22
123 – Mealy 011 Overlapping Sequence Detector
01:31
124 – Mealy 000 Overlapping Sequence Detector
01:45
125 – Mealy 0101 Overlapping Sequence Detector
02:25
126 – Mealy 11011 Overlapping Sequence Detector
02:39
127 – Designing a Mealy Machine Sequence Detector
15:45
128 – Moore 101 NonOverlapping Sequence Detector
04:20
129 – Moore 010 NonOverlapping Sequence Detector
02:26
130 – Moore 0101 NonOverlapping Sequence Detector
02:59
131 – Moore 101 Overlapping Sequence Detector
02:36
132 – Moore 010 Overlapping Sequence Detector
02:09
133 – Moore 0101 Overlapping Sequence Detector
02:30
134 – Designing a Moore Machine Sequence Detector
08:42
135 – Designing a Machine to Pick a Series of Coloured Balls and a Vending Machine
12:13
1 – Introduction
Verilog HDL: VLSI Hardware Design Comprehensive Masterclass
About Lesson

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